Autor: | Bernard Goossens |
Lehekülgede arv: | 439 |
Ilmumisaasta: | 2023 |
Kauba ID: | 17383649 |
The book presents a succession of RISC-V processor implementations in increasing difficulty (non pipelined, pipelined, deeply pipelined, multithreaded, multicore).Each implementation is shown as an HLS (High Level Synthesis) code in C++ which can really be synthesized and tested on an FPGA based development board (such a board can be freely obtained from the Xilinx University Program targeting the university professors).The book can be useful for three reasons. First, it is a novel way to introduce computer architecture. The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promised to become the machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the High Level Synthesis, a tool which is able to translate a C program into an IP (Intellectual Property). Hence, the book can serve to engineers willing to implement processors on FPGA and to researchers willing to develop RISC-V based hardware simulators.
Kauba ID: | 17383649 |
Kategooria: | Majandusalased raamatud |
Tootepakendite arv: | 1 tk. |
Paki suurus ja kaal (1): | 0,03 x 0,16 x 0,24 m, 0,87 kg |
Kirjastus: | Springer International Publishing AG |
Raamatu keel: | Inglise keel |
Tüüp: | Infotehnoloogia |
Autor: | Bernard Goossens |
Lehekülgede arv: | 439 |
Ilmumisaasta: | 2023 |
Toodete pildid on illustratiivsed ja näitlikud. Tootekirjelduses sisalduvad videolingid on ainult informatiivsetel eesmärkidel, seega võib neis sisalduv teave erineda tootest endast. Värvid, märkused, parameetrid, mõõtmed, suurused, funktsioonid, ja / või originaaltoodete muud omadused võivad nende tegelikust väljanägemisest erineda, seega palun tutvuge tootekirjeldustes toodud tootespetsifikatsioonidega.